Adjustable 3D capacitor

ABSTRACT

There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

FIELD OF THE INVENTION

[0001] The invention relates to the general field of integrated circuitswith particular reference to variable capacitors occupying minimum chipreal estate.

BACKGROUND OF THE INVENTION

[0002] LC or RC matching of networks is critical for some analog or RFcircuits. Adjustment of capacitor values after the circuits are alreadyin use is not possible. Once the capacitor value has been pre-set,subsequent fine tuning is not possible and an entirely new mask isneeded for the capacitor portions of the circuit. Additionally,conventional flat capacitor designs tend to occupy large amounts of chipreal estate, acting as a bottleneck for further circuit densification.

[0003] In the pre-integrated circuit era, one of the ways of providingan adjustable capacitor was the layout schematically shown in FIG. 1.Seen there are four top electrodes 15 that share a common lowerelectrode 11. By means of switches 16 the top electrodes can beconnected in parallel, as needed to provide a capacitance value between1 and 9 units between points A and B since, as can be seen, the ratiosof the individual top electrode areas are 5:2:1:1.

[0004] The present invention discloses how the schematic circuit of FIG.1 can be implemented in an integrated circuit, with minimum consumptionof chip real estate.

[0005] A routine search of the prior art was performed with thefollowing references of interest being found:

[0006] In U.S. Pat. No. 5,350,705, Brassington et al. show a flatcapacitor arrangement with common top plate. Aitken et al. in U.S. Pat.No. 6,088,258 shows a planarized interweave capacitor. In U.S. Pat. No.5,604,145, Hashizume et al. disclose a planar capacitor process while inU.S. Pat. No. 5,744,385, Bojabri reveals a compensation technique for aparasitic capacitor.

SUMMARY OF THE INVENTION

[0007] It has been an object of at least one embodiment of the presentinvention to provide a capacitor for use in micro-electronic circuits.

[0008] Another object of at least one embodiment of the presentinvention has been that said capacitor be adjustable at the time thatsaid micro-electronic circuits are being manufactured.

[0009] Still another object of at least one embodiment of the presentinvention has been that said capacitor be adjustable at the time thatsaid micro-electronic circuits are being used in the field.

[0010] A further object of at least one embodiment of the presentinvention has been to provide a process for manufacturing saidadjustable capacitor.

[0011] These objects have been achieved by forming a set of individualcapacitors that share a common bottom electrode. The areas of the topelectrodes of these individual capacitors are chosen to be in anintegral ratio to one another so that they can be combined to produceany capacitance within a range of unit values. For example, if fourcapacitors whose areas are in the ratio of 5:2:1:1, are provided, thenany capacitance in a range of from 1 to 9 can be generated, depending onhow the top electrodes are connected. Such connections can be hard-wiredwithin the final wiring level to provide a factory adjustable capacitoror they can be connected through field programmable devices to produce afield programmable capacitor,

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 shows how a group of capacitors can be connected to providea wide range of capacitances.

[0013]FIG. 2 shows the starting point for the process of the presentinvention.

[0014]FIGS. 3 and 4 shows how several microcapacitors may be formedwithout using up too much chip real estate.

[0015]FIG. 5 shows how connections are made to the individualcapacitors.

[0016]FIG. 6 shows the circuit of FIG. 1 modified to produce a specificcapacitance value.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] We will disclose the present invention through a description ofthe process of the present invention. In the course of so doing, thestructure of the present invention will also become apparent.

[0018] Referring now to FIG. 2, the process of the present inventionbegins with the provision of suitable substrate 21 on which is alreadypresent (or is to be added) an electrical circuit of some kind includingcontact pads, such as 26, to which a capacitor is to be connected. Mostcommonly, though not necessarily exclusively, this will be the topmostlayer of an integrated circuit on a silicon wafer.

[0019] A base dielectric layer 22 is then deposited onto 21 and contactpad 26. Layer 22 could be any of several materials such as siliconoxide, TEOS (tetraethyl orthosilicate), or black diamond (methyl-dopedporous silica), with any material having a low dielectric constant beingpreferred, and it is deposited to a thickness between about 1,000 and10,000 Angstroms, with 2,000 being typical. This is followed by layingdown etch stop layer 25 on layer 22. This layer is typically siliconnitride, but other materials such as silicon carbide could also havebeen used. It is deposited to a thickness between about 10 and 1,000Angstroms following which second dielectric layer 23 is deposited on it.We will refer to layer 23 as a support dielectric layer.

[0020] We have usually used an oxide such as silicon oxide or TEOS forthe support dielectric layer but other materials such as black diamondor silicon carbide could also have been used. It is deposited to athickness between about 1,000 and 5,000 microns. Next, via hole 27 isetched through support dielectric layer 23 as well as etch stop layer 25and base dielectric layer 22, thereby exposing contact pad 26.

[0021] After deposition of a barrier layer (not shown) in via hole 27 itis overfilled with tungsten and then planarized so as to remove alltungsten not inside via 27, resulting in the formation of tungsten via35 (FIG. 3). Then, as seen in FIG. 2, three trenches 24, that extendthrough layer 23 as far as etch stop layer 25, are etched. The presenceof layer 25 ensures that all trenches have exactly the same depth. Eachtrench has a width between about 0.1 and 0.8 microns and the trenchesare separated from one another by between about 0.1 and 1 microns,depending on technology design rules.

[0022] Referring now to FIG. 3, metal layer 11 is then deposited overthe surface of layer 23, using a conformal deposition method such asPECVD (plasma enhanced chemical vapor deposition) to ensure that itsthickness is uniform everywhere, including the floors and walls of thetrenches. Our preferred metal for layer 11 has been Al, but other metalssuch as Ti or TiN could also have been used. Layer 11 is deposited to athickness between about 100 and 3,000 Angstroms and is then patterned toform a common capacitor electrode (see FIG. 1) that is in contact withtungsten via 35.

[0023] This is followed by the deposition of high dielectric constantmaterial layer 32 on common capacitor electrode 11 and then patterninglayer 32 to make sure that it fully overlaps common capacitor electrode11. Examples of layer 32 material include, but are not limited to,silicon nitride, tantalum oxide, hafnium oxide, and aluminum oxide. Itwas deposited to a thickness between about 30 and 300 Angstroms.

[0024] We refer now to FIG. 4. Metal layer 15 is deposited on highdielectric constant layer 32 and then patterned to form four unconnectedtop electrodes 151, 152, and 155, all of whom are overlapped by commonelectrode 11. These correspond to the four capacitors marked 1, 1, 2,and 5 shown schematically in FIG. 1 so their relative areas are arrangedto be in the ratio 1:1:2:5. Materials and thicknesses for layer 15 aresimilar to what was used for layer 11.

[0025] Referring next to FIG. 5, top dielectric layer 53 is thendeposited on layer 15 (as well as any exposed parts of layer 32) andfour via holes 16 are etched through layer 23 so as to expose contactarea for each of top electrodes 151, 152, and 155. Via holes 16 are thenfilled with tungsten as already described above so as to providecontacts such as 54 for connection to the capacitor top plates.

[0026] The process of the present invention concludes by describing twopossible embodiments that differ in how final connections are made tothe capacitor top electrodes. For example, to provide a capacitor havinga value of 6 units of capacitance, connections 61 and 62 need to beclosed, as shown in FIG. 6.

[0027] In a first embodiment a metal layer (not shown) is laid down onlayer 23 and then patterned to make permanent (hard-wired) connectionsto electrode 155 and either of the electrodes 151. In a secondembodiment, a contact wire (not shown) is provided near each contact,such as 54, and then connected to it through a field programmabledevice. This results in a field programmable capacitor whose value canbe adjusted at the time that it is needed in the field. Examples ofpossible field programmable devices include fusible links, anti-fuses,resistors, capacitors, and pass transistors.

[0028] We conclude our description of the present invention by notingthat we have elected to vary capacitance values by introducingdifferences in area. This could also have been accomplished by use ofmore than one dielectric film thickness, by use of more than onedielectric material (each having different dielectric constants), or byany combination of these three possibilities.

What is claimed is:
 1. A process for forming an adjustable capacitor,comprising: providing a silicon wafer having a topmost layer on whichare contact pads connected to a circuit contained in said wafer;depositing a base dielectric layer on said topmost layer, including saidcontact pads; depositing an etch stop layer on said base dielectriclayer; depositing a support dielectric layer on said etch stop layer;etching a via hole through said support dielectric layer, said etch stoplayer, and said base dielectric layer, thereby exposing said contactpad; depositing a barrier layer in said via hole, then overfilling saidvia hole with tungsten and then planarizing so as to remove all tungstennot inside said via; etching three trenches that extend through saidsupport dielectric layer as far as said etch stop layer; depositing afirst layer of metal on said support dielectric layer, including insidesaid trenches, and then patterning said first metal layer to form acommon capacitor electrode that contacts said tungsten-filled via hole;depositing a layer of high dielectric constant material on said commoncapacitor electrode and then patterning said high dielectric constantlayer whereby it fully overlaps said common capacitor electrode;depositing a second layer of metal on said high dielectric constantlayer and then patterning said second metal layer to form fourunconnected top electrodes, all of whom are overlapped by said commonelectrode, said top electrodes having, relative to one another, areas inthe ratio 5:2:1:1; depositing a top dielectric layer on said topelectrodes and said high dielectric constant layer; etching four viaholes through said top dielectric layer whereby a contact area isexposed for each of said top electrodes; depositing a barrier layer insaid via holes, then overfilling said via holes with tungsten and thenplanarizing so as to remove all tungsten not inside said via holes; andthen depositing and patterning a third metal layer so as to providepermanent connections between said top electrodes, thereby giving saidadjustable capacitor a specific capacitance value.
 2. The processdescribed in claim 1 wherein said base dielectric layer is selected fromthe group consisting of silicon oxide, TEOS, black diamond, and alldielectrics having a dielectric constant less than about 5 and said basedielectric layer is deposited to a thickness between about 200 and 5,000Angstroms.
 3. The process described in claim 1 wherein said etch stoplayer is selected from the group consisting of silicon nitride andsilicon carbide and is deposited to a thickness between about 20 and 500microns.
 4. The process described in claim 1 wherein said supportdielectric layer is selected from the group consisting of silicon oxide,black diamond, and all dielectrics having a dielectric constant lessthan about 5 and said support dielectric layer is deposited to athickness between about 200 and 5,000 Angstroms.
 5. The processdescribed in claim 1 wherein said metal layers are selected from thegroup consisting of Al, Ti, TiN, and all metals whose resistivity isless than about 5 microhm-cm, and are deposited to a thickness betweenabout 200 and 5,000 Angstroms.
 6. The process described in claim 1wherein said layer of high dielectric constant material is selected fromthe group consisting of silicon nitride, tantalum oxide, aluminum oxide,and hafnium oxide and is deposited to a thickness between about 20 and500 Angstroms.
 7. The process described in claim 1 wherein each trenchhas a width between about 0.1 and 0.8 microns and said trenches areseparated from one another by between about 0.1 and 0.8 microns.
 8. Aprocess for forming a field programmable capacitor, comprising:providing a silicon wafer having a topmost layer on which are contactpads connected to a circuit contained in said wafer; depositing a basedielectric layer on said topmost layer, including said contact pads;depositing an etch stop layer on said base dielectric layer; depositinga support dielectric layer on said etch stop layer; etching a via holethrough said support dielectric layer, said etch stop layer, and saidbase dielectric layer, thereby exposing said contact pad; depositing abarrier layer in said via hole, then overfilling said via hole withtungsten and then planarizing so as to remove all tungsten not insidesaid via; etching three trenches that extend through said supportdielectric layer as far as said etch stop layer; depositing a firstlayer of metal on said support dielectric layer, including inside saidtrenches, and then patterning said first metal layer to form a commoncapacitor electrode that contacts said tungsten-filled via hole;depositing a layer of high dielectric constant material on said commoncapacitor electrode and then patterning said high dielectric constantlayer whereby it fully overlaps said common capacitor electrode;depositing a second layer of metal on said high dielectric constantlayer and then patterning said second metal layer to form fourunconnected top electrodes, all of whom are overlapped by said commonelectrode, said top electrodes having, relative to one another, areas inthe ratio 5:2:1:1; depositing a top dielectric layer on said topelectrodes and said high dielectric constant layer; etching four viaholes through said top dielectric layer whereby a contact area isexposed for each of said top electrodes; depositing a barrier layer insaid via holes, then overfilling said via holes with tungsten and thenplanarizing so as to remove all tungsten not inside said via holes; andthen depositing and patterning a third metal layer to form a contactwire for each of said filled via holes; and connecting said contactingwires to each other through field programmable devices, thereby formingsaid field programmable capacitor.
 9. The process described in claim 8wherein said field programmable devices are selected from the groupconsisting of fusible links, anti-fuses, pass transistors, resistors,and capacitors.
 10. The process described in claim 8 wherein said basedielectric layer is selected from the group consisting of silicon oxide,black diamond, and all dielectrics having a dielectric constant lessthan about 5 and said base dielectric layer is deposited to a thicknessbetween about 200 and 5,000 Angstroms.
 11. The process described inclaim 8 wherein said etch stop layer is selected from the groupconsisting of silicon nitride and silicon carbide and is deposited to athickness between about 20 and 500 microns.
 12. The process described inclaim 8 wherein said support dielectric layer is selected from the groupconsisting of silicon oxide, black diamond, and all dielectrics having adielectric constant less than about 5 and said support dielectric layeris deposited to a thickness between about 200 and 5,000 Angstroms. 13.The process described in claim 8 wherein said metal layers are selectedfrom the group consisting of Al, Ti, TiN, and all metals whoseresistivity is less than about 5 microhm-cm, and are deposited to athickness between about 200 and 5,000 Angstroms.
 14. The processdescribed in claim 8 wherein said layer of high dielectric constantmaterial is selected from the group consisting of silicon nitride,tantalum oxide, aluminum oxide, and hafnium oxide and is deposited to athickness between about 20 and 500 Angstroms.
 15. The process describedin claim 8 wherein each trench has a width between about 0.1 and 0.8microns and said trenches are separated from one another by betweenabout 0.1 and 0.8 microns.
 16. An adjustable capacitor, comprising: asilicon wafer having a topmost layer on which are contact pads connectedto a circuit contained in said wafer; a base dielectric layer on saidtopmost layer and said contact pads; an etch stop layer on said basedielectric layer; a support dielectric layer on said etch stop layer; atungsten via, extending through said support dielectric layer, said etchstop layer, and said base dielectric layer, and contacting said contactpad; three trenches that extend through said support dielectric layer asfar as said etch stop layer; a common capacitor electrode on saidsupport dielectric layer, including inside said trenches, that contactssaid tungsten via; on said common capacitor electrode, a layer of highdielectric constant materia that fully overlaps said common capacitorelectrode; on said high dielectric constant layer, four unconnected topelectrodes, all of whom are overlapped by said common electrode, saidtop electrodes having, relative to one another, areas in the ratio5:2:1:1; a top dielectric layer on said top electrodes and said highdielectric constant layer; four tungsten vias, extending through saidtop dielectric layer, that contact each top electrode, one such via perelectrode; and on said top dielectric layer, permanent electricalconnections between said top electrodes, whereby said adjustablecapacitor has a specific capacitance value.
 17. The capacitor describedin claim 16 wherein said base dielectric layer is selected from thegroup consisting of silicon oxide, black diamond, and all dielectricshaving a dielectric constant less than about 5 and said base dielectriclayer is deposited to a thickness between about 200 and 5,000 Angstroms.18. The capacitor described in claim 16 wherein said etch stop layer isselected from the group consisting of silicon nitride and siliconcarbide and is deposited to a thickness between about 20 and 500microns.
 19. The capacitor described in claim 16 wherein said supportdielectric layer is selected from the group consisting of silicon oxide,black diamond, and all dielectrics having a dielectric constant lessthan about 5 and said support dielectric layer is deposited to athickness between about 200 and 5,000 Angstroms.
 20. The capacitordescribed in claim 16 wherein said common capacitor electrode and saidtop electrodes are a metal selected from the group consisting of Al,AlCu, Cu, Ti, TiN, and Ta and have a thickness between about 200 and5,000 Angstroms.
 21. The capacitor described in claim 16 wherein saidlayer of high dielectric constant material is selected from the groupconsisting of silicon nitride, tantalum oxide, aluminum oxide, andhafnium oxide and is deposited to a thickness between about 20 and 500Angstroms.
 22. The capacitor described in claim 16 wherein each trenchhas a width between about 0.1 and 0.8 microns and said trenches areseparated from one another by between about 0.1 and 0.8 microns.
 23. Afield programmable capacitor, comprising: a silicon wafer having atopmost layer on which are contact pads connected to a circuit containedin said wafer; a base dielectric layer on said topmost layer and saidcontact pads; an etch stop layer on said base dielectric layer; asupport dielectric layer on said etch stop layer; a tungsten via,extending through said support dielectric layer, said etch stop layer,and said base dielectric layer, and contacting said contact pad; threetrenches that extend through said support dielectric layer as far assaid etch stop layer; a common capacitor electrode on said supportdielectric layer, including inside said trenches, that contacts saidtungsten via; on said common capacitor electrode, a layer of highdielectric constant materia that fully overlaps said common capacitorelectrode; on said high dielectric constant layer, four unconnected topelectrodes, all of whom are overlapped by said common electrode, saidtop electrodes having, relative to one another, areas in the ratio5:2:1:1; a top dielectric layer on said top electrodes and said highdielectric constant layer; four tungsten vias, extending through saidtop dielectric layer, that contact each top electrode, one such via perelectrode; and on said top dielectric layer, a metallic contact wire foreach of said filled via holes, said contact wires being connectable toeach other through field programmable devices.
 24. The capacitordescribed in claim 23 wherein said field programmable devices areselected from the group consisting of fusible links, anti-fuses, andpass transistors.
 25. The capacitor described in claim 23 wherein saidbase dielectric layer is selected from the group consisting of siliconoxide, black diamond, and all dielectrics having a dielectric constantless than about 5 and said base dielectric layer is deposited to athickness between about 200 and 5,000 Angstroms.
 26. The capacitordescribed in claim 23 wherein said etch stop layer is selected from thegroup consisting of silicon nitride and silicon carbide and is depositedto a thickness between about 20 and 500 microns.
 27. The capacitordescribed in claim 23 wherein said support dielectric layer is selectedfrom the group consisting of silicon oxide, black diamond, and alldielectrics having a dielectric constant less than about 5 and saidsupport dielectric layer is deposited to a thickness between about 200and 5,000 Angstroms.
 28. The capacitor described in claim 23 whereinsaid common capacitor electrode and said top electrodes are a metalselected from the group consisting of Al, AlCu, Cu, Ti, TiN, and Ta andhave a thickness between about 200 and 5,000 Angstroms.
 29. Thecapacitor described in claim 23 wherein said layer of high dielectricconstant material is selected from the group consisting of siliconnitride, tantalum oxide, aluminum oxide, and hafnium oxide and isdeposited to a thickness between about 20 and 500 Angstroms.
 30. Thecapacitor described in claim 23 wherein each trench has a width betweenabout 0.1 and 0.8 microns and said trenches are separated from oneanother by between about 0.1 and 0.8 microns.